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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2005, zarlink semiconductor inc. all rights reserved. features ?st-bus ? compatible ? transmit/receive filters & pcm codec in one i.c ? meets at&t d3/d4 and ccitt g711 and g712 ? -law: mt8960/62/64/67 ? a-law: mt8961/63/65/67 ? low power consumption: op.: 30 mw typ. stby.: 2.5 mw typ. ? digital coding options: mt8964/65/66/67 ccitt code mt8960/61/62/63 alternative code ? digitally controlled gain adjust of both filters ? analog and digital loopback ? filters and codec independently user accessible for testing ? powerdown mode available ? 2.048 mhz master clock input ? up to six uncommitted control outputs ? 5 v 5% power supply description manufactured in iso 2 -cmos, these integrated filter/codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., pabx, central office, digital telephones. november 2005 ordering information mt8960/61/64/65ae 18 pin pdip tubes mt8962/63ae 20 pin pdip tubes mt8962/63/66/67as 20 pin soic tubes mt8963/66asr 20 pin soic tape & reel mt8960/64/65ae1 18 pin pdip* tubes mt8961ae1 18 pin pdip* tubes MT8962ASR1 20 pin soic* tape & reel mt8962/63ae1 20 pin pdip* tubes mt8962/66as1 20 pin soic* tubes mt8963as1 20 pin soic* tubes mt8963asr1 20 pin soic* tape & reel mt8967as1 20 pin soic* tubes mt8966/67asr1 20 pin soic* tape & reel *pb free matte tin -40 c to +85 c iso 2 -cmos mt8960/61/62/63/64/65/66/67 integrated pcm filter codec data sheet figure 1 - functional block diagram anul v x sd0 sd1 sd2 sd3 sd4 sd5 v r v ref gnda gndd v dd v ee dsto csti ca f1i c2i dsti transmit filter output register receive filter analog to digital pcm encoder pcm digital to analog decoder output register input register a register 8-bits b-register 8-bits control logic
mt8960/61/62/63/64/65/66/67 data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin name description csti control st-bus in is a ttl-compatible digital input used to control the functi on of the filter/codec. three modes of operation may be effected by applying to this input a logic high (v dd ), logic low (gndd), or an 8-bit serial word, depending on the logic states of ca and f1i . functions controlled are: powerdown, filter gain adjust, loopback, chip testing, sd outputs. dsti data st-bus in accepts the incoming 8-bit pcm word. input is ttl-compatible. c2i clock input is a ttl-compatible 2.048 mhz clock. dsto data st-bus out is a three-state digital output driving the pcm bus with the outgoing 8-bit pcm word. v dd positive power supply (+5 v). f1i synchronization input is an active low digital input enabli ng (in conjunction with ca) the pcm input, pcm output and digital control input. it is interna lly sampled on every positive edge of the clock, c2i, and provides frame and channel synchronization. ca control address is a three-level digital input which enabl es pcm input and output and determines into which control register (a or b) the serial data, presented to csti, is stored. sd3 system drive output is an open drain output of an n-channel tran sistor which has its source tied to gnda. inactive state is open circuit. sd4-5 system drive outputs are open drain outputs of n-channel transi stors which have their source tied to gndd. inactive st ate is open circuit. sd0-2 system drive outputs are ?totempole? cmos outputs switching between gndd and v dd . inactive state is logic low. v ee negative power supply (-5 v). v x voice transmit is the analog input to the transmit filter. anul auto null is used to integrate an internal auto-null signal. a 0.1 f capacitor must be connected between this pin and gnda. v r voice receive is the analog output of the receive filter. gnda analog ground (0 v). v ref voltage reference input to d to a converter. gndd digital ground (0 v). 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 20 pin pdip/soic csti dsti c2i dsto vdd sd5 sd4 f1i ca sd3 gndd vref gnda vr anul vx vee sd0 sd1 sd2 1 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 18 pin pdip csti dsti c2i dsto vdd f1i ca sd3 sd2 gndd vref gnda vr anul vx vee sd0 sd1 mt8960/61/64/65 mt8962/63/66/67
mt8960/61/62/63/64/65/66/67 data sheet 3 zarlink semiconductor inc. figure 3 - -law encoder transfer characteristic 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 10000000 10001111 10011111 10101111 10111111 11001111 11011111 11101111 11111111 01111111 01101111 01011111 01001111 00111111 00101111 00011111 00001111 00000000 -2.415v -1.207v 0v +1.207v +2.415v bit 7... 0 msb lsb analog input voltage (v in ) mt8960/62 digital output mt8964/66 digital output
mt8960/61/62/63/64/65/66/67 data sheet 4 zarlink semiconductor inc. figure 4 - a-law encoder transfer characteristic functional description figure 1 shows the functional block diagram of the mt 8960-67. these devices provide the conversion interface between the voiceband analog signals of a telephone subscriber loop and the di gital signals required in a digital pcm (pulse code modulation) switchi ng system. analog (voiceband) signals in the transmit path enter the chip at v x , are sampled at 8 khz, and the samples quantized and assi gned 8-bit digital values defined by logarithmic pcm encoding laws. analog signals in the receive path leave the chip at v r after reconstruction from digital 8-bit words. separate switched capacitor filter sections are used for bandlimiting prior to digital encoding in the transmit path and after digital decoding in the receive path. all filter clocks are derived from the 2.048 mhz master clock input, c2i. chip size is minimized by the use of common ci rcuitry performing the a to d and d to a conversion. a successive approximation technique is used with capacito r arrays to define the 16 steps and 8 chords in the signal conversion process. eight-bit pcm encoded digital da ta enters and leaves the chip serially on dsti and dsto pins, respectively. transmit path analog signals at the input (vx) are fi rstly bandlimited to 508 khz by an rc lowpass filter section. this performs the necessary anti-aliasing for the followi ng first-order sampled data lowpass pre- filter which is clocked at 512 khz. this further bandlimits the signal to 124 khz before a fift h-order elliptic lowpass filter, clocked at 128 khz, provides the 3.4 khz bandwidth required by the encoder section. a 50/60 hz third-order highpass notch filter clocked at 8 khz completes the transmit filter path. accumulated dc of fset is cancelled in this last section by a switched- capacitor auto-zero loop which integrates the sign bit of the encoded pcm word, fed back from the codec and 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 10101010 10100101 10110101 10000101 10010101 11100101 11110101 11000101 11010101 01010101 01000101 01110101 01100101 00010101 00000101 00110101 00100101 00101010 -2.5v -1.25v 0v +1.25v +2.5v bit 7... 0 msb lsb analog input voltage (v in ) mt8961/63 digital output mt8965/67 digital output
mt8960/61/62/63/64/65/66/67 data sheet 5 zarlink semiconductor inc. injects this voltage level into the non-inverting input of the comparator. an integrating capacitor (of value between 0.1 and 1 f) must be externally connected from th is point (anul) to the analog ground (gnda). the absolute gain of the transmit filter (nominally 0 db at 1 khz) can be adjusted from 0 db to 7 db in 1 db steps by means of three binary controlled gain pads. the resulting bandpass characteristics with the limits shown in figure 10 meet the ccitt and at&t recommended specifications. typical attenuat ions are 30 db for 0-60 hz and 35 db for 4.6 khz and above. the filter output signal is an 8 khz staircase waveform whic h is fed into the codec capacitor array, or alternatively, into an external capacitive load of 250 pf when the chip is in the test mode. the digital encoder generates an eight- bit digital word representation of the 8 k hz sampled analog signal. the first bit of serial data stream is bit 7 (msb) and represents the sign of the analog signal. bits 4-6 represent the chord which contains the analog sample value. bits 0-3 represent the step value of the analog sample within the select ed chord. the mt8960-63 provide a sign plus magnitude pcm output code format. the mt8964/ 66 pcm output code conforms to the at &t d3 specification, i.e., true sign bit and inverted magnitude bits. the mt8965/67 pcm output code conforms to the ccitt specifications with alternate digit inversion (even bi ts inverted). see figs. 3 and 4 for the digital output code corresponding to the analog voltage, v in , at v x input. the eight-bit digital word is output at dsto at a nominal rate of 2.048 mhz, vi a the output buffer as the first 8-bits of the 125 s sampling frame. receive path an eight-bit pcm encoded digital word is re ceived on dsti input once during the 125 s period and is loaded into the input register. a charge proportional to the received pcm word appears on the capacitor array and an 8 khz sample and hold circuit integrates this charge an d holds it for the rest of the sampling period. the receive (d/a) filter provides interp olation filtering on the 8 khz sample and hold signal from the codec. the filter consists of a 3.4 khz lowpass fifth-order elliptic se ction clocked at 128 khz and performs bandlimiting and smoothing of the 8 khz "staircase" waveform. in additi on, sinx/x gain correction is applied to the signal to compensate for the attenuation of hi gher frequencies caused by the capaci tive sample and hold circuit. the absolute gain of the receive filter can be adjusted from 0 db to -7 db in 1 db steps by means of three binary controlled gain pads. the resulting lowpa ss characteristics, with the limits show n in figure 11, meet the ccitt and at & t recommended specifications. typical attenuation at 4.6 khz and above is 30 db. the filt er is followed by a buffer amplifier which will drive 5v peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits. v ref an external voltage must be supplied to the v ref pin which provides the reference voltage for the digital encoding and decoding of the analog signal. for v ref = 2.5 v, the digital encode decision value for overload (maximum analog signal detect level) is equal to an analog input v in = 2.415 v ( -law version) or 2.5 v (a-law version) and is equivalent to a signal level of 3.17 dbm0 or 3.14 dbm0 respectively, at the codec. the analog output voltage from the decoder at v r is defined as: -law: -0.5 2 c 16.5 + s v ref x [( 128 ) + ( 128 )( 33 )] v offset a-law: 2 c+1 0.5 + s v ref x [( 128 )( 32 )] v offset c=0
mt8960/61/62/63/64/65/66/67 data sheet 6 zarlink semiconductor inc. 2 c 16.5 + s v ref x [( 128 )( 32 )] v offset c 0 where c = chord number (0-7) s = step number (0-15) v ref is a high impedance input with a varying capacitive load of up to 40 pf. the recommended reference voltage for the mt8960 series of codecs is 2.5 v 0.5%. the output voltage from the reference source should have a maximum temperature coefficient of 100 ppm/c . this voltage should have a total regulation tolerance of 0.5% both for changes in the input voltage and output loading of the voltage reference source. a voltage reference circuit ca pable of meeting these specificati ons is shown in figure 5. analog devices?ad1403a voltage reference circuit is capable of driving a large number of codecs due to the high input impedance of the v ref input. normal precautions should be taken in pcb layout design to minimize noise coupling to this pin. a 0.1 f capacitor connected from v ref to ground and located as close as possible to the codec is recommended to minimize noise entering through v ref . this capacitor should have good high frequency characteristics. figure 5 - typical voltage reference circuit timing the codec operates in a synchronous manner (see figure 9a). the codec is activated on the first positive edge of c2i after f1i has gone low. the digital output at dsto (whi ch is a three-state output driver) will then change from a high impedance state to the sign bit of the encoded pcm word to be output. this will remain valid until the next positive edge, when the next most significant bit will be output. on the first negative clock edge (after f1i signal has been internally synchronized and ca is at gndd or v ee ) the logic signal present at dsti will be cl ocked into the input shift register as the sign bit of the incoming pcm word. the eight-bit word is thus input at dsti on negativ e edges of c2i and output at dsto on positive edges of c2i. f1i must return to a high level after the eighth clock pulse causing dsto to enter high impedance and preventing further input data to dsti. f1i will continue to be sampled on ever y positive edge of c2i. (note: f1i may subsequently be taken low during the same sampling fram e to enable entry of serial data into csti. this occurs usually mid-frame, in conjunction with ca=v dd , in order to enter an 8-bit control wo rd into register b. in this case, pcm input and output are inhibited by ca at v dd .) internally the codec will then perform a decode cycl e on the newly input pcm word. the sampled and held analog signal thus decoded will be updated 25 s from the start of the cycle. after th is the analog input from the filter is sampled for 18 s, after which digital conversion ta kes place during the remaining 82 s of the sampling cycle. nc 1234 5 6 7 8 ad1403a +5 v 2.5 v 0.1 f v ref mt8960-67 filter/codec nc nc nc nc
mt8960/61/62/63/64/65/66/67 data sheet 7 zarlink semiconductor inc. since a single clock frequency of 2.048 mhz is required, a ll digital data is input and output at this rate. dsto, therefore, assumes a high im pedance state for all but 3.9 s of the 125 s frame. similarly, dsti input data is valid for only 3.9 s. digital control functions csti is a digital input (levels gndd to v dd ) which is used to control the functi on of the filter/codec. it operates in three different modes depending on the logic levels applied to the control a ddress input (ca) and chip enable input (f1i ) (see table 1). mode 1 ca=-5v (v ee ); csti=0v (gndd) the filter/codec is in normal operation with nominal transmit and receive gain of 0db. the sd outputs are in their active states and the test modes cannot be entered. ca = -5v (v ee ); csti = +5v (v dd ) a state of powerdown is forced upon the chip whereby dsto becomes high impedance, v r is connected to gnda and all analog sections have power removed. mode 2 ca= -5v (v ee ); csti receives an eight-bit control word csti accepts a serial data stream synchronously with dsti (i.e., it accepts an eight-b it serial word in a 3.9 s timeslot, updated every 125 s, and is specified identically to dsti for ti ming considerations). this eight-bit control word is entered into control register a and enables progr amming of the following func tions: transmit and receive gain, powerdown, loopback. register b is reset to zero and the sd outputs assume their inactive state. test modes cannot be entered. mode 3 ca=0v (gndd); csti receives an eight-bit control word as in mode 2, the control word enters register a and t he aforementioned functions ar e controlled. in this mode, however, register b is not reset, thus not affecting the stat es of the sd outputs. ca=+5v (v dd ); csti receives an 8-bit control word in this case the control word is transferred into regist er b. register a is unaffect ed. the input and output of pcm data is inhibited. the contents of register b controls the six unco mmitted outputs sd0-sd5 (four outputs, sd0-sd3, on mt8960/61/64/65 versions of chip) and also provide ent ry into one of the three test modes of the chip. note: for modes 1 and 2, f1i must be at logic lo w for one period of 3.9 s, in each 125 s cycle, when pcm data is being input and output, and the control word at csti enters register a. for mode 3, f1i must be at a logic low for two periods of 3.9 s, in each 125 s cycle. in the first period, ca must be at gndd or v ee , and in the second period ca must be high (v dd) .
mt8960/61/62/63/64/65/66/67 data sheet 8 zarlink semiconductor inc. table 1 - digital control modes mode ca csti function 1 (note 1) v ee gndd normal chip operation. v dd powerdown. 2v ee serial eight-bit control word into register a. register b is reset. data 3 (note 2) gndd serial eight-bit control word into register a. register b is unaffected. data v dd serial eight-bit control word into register a. register b is unaffected. data note 1: when operating in mode 1, there should be only one frame pulse (f1i ) per 125 s frame note 2: when operating in mode 3, pcm in put and output is inhibited by ca=v dd . bit 2 bit 1 bit 0 transmit (a/d) filter gain (db) 000 0 001 + 1 010 + 2 011 + 3 100 + 4 101 + 5 110 + 6 111 + 7 bit 5 bit 4 bit 3 receive (d/a) filter gain (db) 000 0 001 - 1 010 - 2 011 - 3 100 - 4 101 - 5 110 - 6 111 - 7
mt8960/61/62/63/64/65/66/67 data sheet 9 zarlink semiconductor inc. table 2 - control states - register a control registers a, b the contents of these registers c ontrol the filter/codec functions as described in tables 2 and 3. bit 7 of the registers is the msb and is defined as the first bit of the serial data stream input (corresponding to the sign bit of the pcm word). on initial power-up these registers are set to the powerdown condition fo r a maximum of 25 clock cycles. during this time it is impossible to change the data in these registers. chip testing by enabling register b with valid data (eight-bit control word input to csti when f1i =gndd and ca= v cc ) the chip testing mode can be entered. bits 6 and 7 (most sign bits) define states for test ing the transmit filter, receive filter and the codec function. the input in each case is v x input and the output in each case is v r output. (see table 3 for details.) loopback loopback of the filter/codec is controlled by the control wo rd entered into register a. bits 6 and 7 (most sign bits) provide either a digital or anal og loopback condition. digital loopback is defined as follows: ? pcm input data at dsti is latched into the pcm input register and the output of this register is connected to the input of the 3-state pcm output register. ? the digital input to the pcm digital-to-analog decoder is disconnected, forced to zero (0). ? the output of the pcm encoder is disabled and thus the encoded data is lost. the pcm output at dsto is determined by the pcm input data. analog loopback is defined as follows: ? pcm input data is latched, decoded and f iltered as normal but not output at v r . ? analog output buffer at v r has its input shorted to gnda and disconnected from the receive filter output. ? analog input at v x is disconnected from the transmit filter input. ? the receive filter output is connected to the transmit fi lter input. thus the decode signal is fed back through the receive path and encoded in the normal way. the analog output buffer at v r is not tested by this configuration. in both cases of loopback, dsti is the input and dsto is the output. bit 7 bit 6 function control 0 0 normal operation 0 1 digital loopback 1 0 analog loopback 1 1 powerdown bit 2 bit 1 bit 0 transmit (a/d) filter gain (db)
mt8960/61/62/63/64/65/66/67 data sheet 10 zarlink semiconductor inc. logic control outputs sd0-5 these outputs are directly controlled by the logic states of bits 0-5 in register b. a logic low (gndd) in register b causes the sd outputs to assume an inactive state. a logic high (v dd ) in register b causes the sd outputs to assume an active state (see table 3). sd0-2 switch between gndd and v dd and may be used to control external logic or transistor circuitry, for exam ple, that employed on the line ca rd for performing such functions as relay drive for application of ringing to line, message waiting indication, etc. sd3-5 are used primarily to drive external analog circuitry. examples may include the switching in or out of gain sections or filter sections (e.g ., ring trip filter) (figure 7). mt8962/63/66/67 provides all six sd outputs. mt8960/61/64/65 each packaged in an 18-pin dip provide only four control outputs, sd0-3. figure 6 - typical line termination bits 0-2 logic control outputs sd 0 -sd 2 0 inactive state - logic low (gndd). 1 active state - logic high (v dd ). bit 3 logic control output sd 3 0 inactive state - high impedance. 1 active state - gnda. bits 4,5 logic control outputs sd 4 , sd 5 0 inactive state - high impedance. 1 active state - gndd. bit 7 bit 6 chip testing controls 0 0 normal operation. telephone set 2 wire analog supervision protection battery feed ringing pcm highway 2w/4w converter mt8960/61 mt8962/63 mt8964/65 mt8966/67
mt8960/61/62/63/64/65/66/67 data sheet 11 zarlink semiconductor inc. table 3 - control states - register b powerdown powerdown of the chip is achieved in several ways: internal control: 1) initial power-up. initial application of v dd and v ee causes powerdown for a period of 25 clock cycles and during this period the chip will acce pt input only from c2i. the b-register is reset to zero forcing sd0-5 to be inactive. bits 0-5 of register a (gain adjust bits ) are forced to zero and bits 6 and 7 of register a become logic high thus reinforcing the powerdown. 2) loss of c2i. powerdown is entered 10 to 40 s after c2i has assumed a continuous logic high (v dd ). in this condition the chip will be in the same state as in (1) above. note: if c2i stops at a continuous logic low (gndd), the digital data and status is indeterminate. external control: 1) register a. powerdown is controlled by bits 6 and 7 (w hen both at logic high) of register a which in turn receives its control word input via csti, when f1i is low and ca input is either at v ee or gndd. power is removed from the filters and analog sections of the chip. the analog output buffer at v r will be connected to gnda. dsto becomes high impeda nce and the clocks to the majority of the logic are stopped. sd outputs are unaffected and may be updated as normal. 2) csti input. with ca at v ee and csti held at continuous logic high the chip assumes the same state as described in external control (1) above. 0 1 transmit filter testing, i.e.: transmit filter input connected to v x input receive filter and buffer disconnected from v r 1 0 receive filter testing, i.e.: receive filter input connected to v x input receive filter input disconnected from codec 1 1 codec testing i.e.: codec analog input connected to v x codec analog input disconnected from transmit filter output codec analog output connected to v r v r disconnected from receive filter output bits 0-2 logic control outputs sd 0 -sd 2
mt8960/61/62/63/64/65/66/67 data sheet 12 zarlink semiconductor inc. figure 7 - typical use of the special drive outputs from st-bus from st-bus master clock to st-bus 5 v alignment register select csti dsti c2i dsto v dd f1i ca sd3 sd2 gndd v ref gnda v r anul v x v ee sd0 sd1 2.5 v 0.1 f -5 v mt8960/61/64/65 gain section 2/4 wire converter message waiting (with relay drive) ring feed (with relay drive) -100 v dc telephone line -48 v dc -48 v dc 90 v rms ring trip filter (with relay drive)
mt8960/61/62/63/64/65/66/67 data sheet 13 zarlink semiconductor inc. figure 8 - example architecture of a simple digital switching system using the mt8960-67 dsti dsto cdti v x v r sd0 sdn . . . ? ? ? repeated for lines 2 to 255 line 1 line 256 8 8 8 8 speech switch - 8980 controlling micro- processor control & signalling - 8980 dsti dsto cdti v x v r sd0 sdn . . . ? ? ? ? ? ? repeated for lines 2 to 255 line interface & monitoring circuitry line interface & monitoring circuitry ? ? ? mt8960-67 mt8960-67
mt8960/61/62/63/64/65/66/67 data sheet 14 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note 1: temperature coefficient of v ref should be better than 100 ppm/ c. absolute maximum ratings* parameter symbol min. max. units 1 dc supply voltages v dd -gndd -0.3 +6.0 v v ee -gndd -6.0 +0.3 v 2 reference voltage v ref gnda v dd v 3 analog input v x v ee v dd v 4 digital inputs except ca gndd-0.3 v dd +0.3 v ca v ee -0.3 v dd +0.3 v 5 output voltage sd 0-2 gndd-0.3 v dd +0.3 v sd 3 v ee -0.3 v dd +0.3 v sd 4-5 v ee -0.3 v dd +0.3 v 6 current on any pin i i 20 ma 7 storage temperature t s -55 +125 c 8 power dissipation at 25 c (derate 16 mw/ c above 75 c) p diss 500 mw recommended operating conditions - voltages are with respect to gndd unless otherwise stated characteristics sym. min. typ.* max. units comments 1 supply voltage v dd 4.75 5.0 5.25 v v ee -5.25-5.0-4.75 v v ref 2.5 v see note 1 2 voltage on digital ground vgndd -0.1 0.0 +0.1 vdc ref. to gnda -0.4 0.0 +0.4 vac ref. to gnda 400 ns max. duration in 125 s cycle 3 operating temperature t o 0+70 c 4 operating current v dd v ee i dd i ee 3.0 3.0 4.0 4.0 ma ma all digital inputs at v dd or gndd (or v ee for ca) v ref i ref 2.0 a mean current 5 standby current v dd v ee i ddo i eeo 0.25 0.25 1.0 1.0 ma ma all digital inputs at v dd or gndd (or v ee for ca)
mt8960/61/62/63/64/65/66/67 data sheet 15 zarlink semiconductor inc. * typical figures are at 25 c with nominal 5v supplies. for design aid only: not guaranteed and not subject to production testing. note 2: v osin specifies the dc component of the digitally encoded pcm word. dc electrical characteristics - voltages are with respect to gndd unless otherwise stated. t a =0 to 70 c, v dd =5v 5%, v ee =-5v 5%, v ref =2.5v 0.5%, gnda=gndd=0v,clock frequency =2.048mhz. outputs unloaded unless otherwise specified. characteristics sym. min. typ. * max. units test conditions 1 d i g i t a l input current except ca i i 10.0 av in = gndd to v dd ca i ic 10.0 av in = v ee to v dd 2 input low except ca v il 0.0 0.8 v voltage ca v ilc v ee v ee +1.2 v 3 input high voltage all inputs v ih 2.4 5.0 v 4 input intermediate ca voltage v iic 0.0 0.8 v 5 output leakage dsto current (tristate) sd 3-5 i 0z 0.1 10.0 a a output high impedance 6 d i g i t a l output low dsto v ol 0.4 v i out =1.6 ma voltage sd 0-2 v ol 1.0 v i out =1 ma 7 output high dsto v oh 4.0 v i out =-100 a voltage sd 0-2 v oh 4.0 v i out =-1ma 8 output resistance sd 3-5 r out 1.0 2.0 k ? v out =+1v 9 output capacitance dsto c out 4.0 pf output high impedance 1 0 a n a l o g input current v x i in 10.0 av ee v in v cc 1 1 input resistance v x r in 10.0 m ? 1 2 input capacitance v x c in 30.0 pf f in = 0 - 4 khz 1 3 input offset voltage v x v osin +1.0 mv see note 2 1 4 output resistance v r r out 100 ? 1 5 output offset voltage v r v oso ut 100 mv digital input= +0
mt8960/61/62/63/64/65/66/67 data sheet 16 zarlink semiconductor inc. (see figures 9a, 9b, 9c) * typical figures are at 25 c with nominal 5v supplies. for design aid only: not guaranteed and not subject to production testing. note 3: the filter characteristics are totally dependent upon the accuracy of the clock frequency providing f1i is synchronized to c2i. the a/d and d/a functions are unaffected by changes in clock frequency. note 4: this gives a 75 ns period, 50 ns before and 25 ns after the 50% point of c2i rising edge, when change in f1i will give an undetermined state to the internally synchronized enable signal. ac electrical characteristics - voltages are with respect to gndd unless otherwise stated. t a =0 to 70 c, v dd =5v 5%, v ee =-5v 5%, v ref =2.5v 0.5%, gnda=gndd=0v, clock frequency=2.048 mhz. outputs unloaded unless otherwise specified. characteristics sym. min. typ. * max units test conditions 1 d i g i t a l clock frequency c2i f c 2.046 2.048 2.05 mhz see note 3 2 clock rise time c2i t cr 50 ns 3 clock fall time c2i t cf 50 ns 4 clock duty cycle c2i 40 50 60 % 5 chip enable rise time f1i t er 100 ns 6 chip enable fall time f1i t ef 100 ns 7 chip enable setup time f1i t es 50 ns see note 4 8 chip enable hold time f1i t eh 25 ns see note 4 9 output rise time dsto t or 100 ns 10 output fall time dsto t of 100 ns 11 propagation delay clock dsto to output enable t pzl t pzh 122 122 ns ns r l =10 k ? to v cc 12 propagation delay dsto clock to output t plh t phl 100 100 ns ns c l =100 pf 13 input rise time csti dsti t ir 100 100 ns ns 14 input fall time csti dsti t if 100 100 ns ns 15 input setup time csti dsti t ish t isl 25 0 ns ns 16 input hold time csti dsti t ih 60 60 ns ns 17 d i g i t a l propagation delay sd clock to sd output t pcs 400 ns c l = 100 pf 18 sd output fall time sd t sf 200 ns c l = 20 pf 19 sd output rise time sd t sr 400 ns 20 digital loopback time dsti to dsto t dl 122 ns
mt8960/61/62/63/64/65/66/67 data sheet 17 zarlink semiconductor inc. ac electrical characteristics - transmit (a/d) path - voltages are with respect to gndd unless otherwise stated. t a =0 to 70 c, v dd =5v 5%, v ee =-5v 5%, v ref =2.5v 0.5%, gnda=gndd=0v, clock frequency = 2.048mhz, filter gain setting = 0db. outputs unloaded unless otherwise specified. characteristics sym. min. typ. * max. units test conditions 1 a n a l o g analog input at v x equivalent to the overload decision level at the codec v in 4.82 9 5.00 0 v pp v pp level at codec: - law: 3.17 dbm0 a-law: 3.14 dbm0 see note 6 2 absolute gain (0db setting) g ax -0.25 +0.25 db 0 dbm0 @ 1004 hz 3 absolute gain (+1db to +7db settings) -0.35 +0.35 db from nominal, @ 1004 hz 4 gain variation with temp g axt 0.01 db t a =0 c to 70 c with supplies g axs 0.04 db/v 5 gain tracking (see figure 12) ccitt g712 (method 1) gt x1 -0.25 -0.25 -0.50 +0.25 +0.25 +0.50 db db db sinusoidal level: +3 to -20 dbm0 noise signal level: -10 to -55 dbm0 -55 to -60 dbm0 ccitt g712 (method 2) at&t gt x2 -0.25 -0.50 -1.50 +0.25 +0.50 +1.50 db db db sinusoidal level: +3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 6 quantization distortion (see figure 13) ccitt g712 (method 1) d qx1 28.00 35.60 33.90 29.30 14.20 db db db db db noise signal level: -3 dbm0 -6 to -27 dbm0 -34 dbm0 -40 dbm0 -55 dbm0 ccitt g712 (method 2) at&t d qx2 35.30 29.30 24.30 db db db sinusoidal input level: 0 to -30 dbm0 -40 dbm0 -45 dbm0 7 idle channel c-message n cx 18 dbrnc0 - law only noise psophometric n px -67 dbm0p ccitt g712 8 single frequency noise n sfx -56 dbm0 ccitt g712 9 harmonic distortion (2nd or 3rd harmonic) -46 db input signal: 0 dbm0 @ 1.02 khz 10 envelope delay d ax 270 s @ 1004 hz 11 envelope delay 1000-2600 hz variation with 600-3000 hz frequency 400-3200 hz d dx 60 150 250 s s s input signal: 400-3200 hz sinewave at 0 dbm0
mt8960/61/62/63/64/65/66/67 data sheet 18 zarlink semiconductor inc. * typical figures are at 25 c with nominal 5v supplies. for design aid only: not guaranteed and not subject to production testing note 6: 0dbm0=1.185 v rms for the - law codec. 0dbm0=1.231 v rms for the a-law codec. a n a l o g quantization ccitt g712 distortion (method 2) (cont?d) at&t (see figure 13) d qx2 35.30 29.30 24.30 db db db sinusoidal input level: 0 to -30 dbm0 -40 dbm0 -45 dbm0 12 intermodulation ccitt g712 distortion 50/60 hz imd x 1 -55 db 50/60 hz @ -23 dbm0 and any signal within 300-3400 hz at -9 dbm0 ccitt g712 2 tone imd x 2 -41 db 740 hz and 1255 hz @ -4 to -21 dbm0. equal input levels at&t imd x 3 -47 db 2nd order products 4 tone imd x 4 -49 db 3rd order products 13 gain relative to 50 hz gain @ 1004 hz 60 hz (see figure 10) 200 hz 300-3000 hz 3200 hz 3300 hz 3400 hz 4000 hz 4600 hz g rx -1.8 - 0.125 - 0.275 - 0.350 -0.80 -25 -30 0.00 0.125 0.125 0.030 - 0.100 -14 -32 db db db db db db db db db 0 dbm0 input signal transmit filter response 14 crosstalk d/a to a/d ct rt -70 db 0 dbm0 @ 1.02 khz in d/a 15 power supply v dd rejection v ee pss r 1 pss r 2 33 35 db db input 50 mv rms at 1.02 khz 16 overload distortion (see fig.15) input frequency=1.02khz ac electrical characteristics - transmit (a/d) path - voltages are with respect to gndd unless otherwise stated. t a =0 to 70 c, v dd =5v 5%, v ee =-5v 5%, v ref =2.5v 0.5%, gnda=gndd=0v, clock frequency = 2.048mhz, filter gain setting = 0db. outputs unloaded unless otherwise specified.
mt8960/61/62/63/64/65/66/67 data sheet 19 zarlink semiconductor inc. ac electrical characteristics - receive (d/a) path - voltages are with respect to gndd unless otherwise stated. t a =0 to 70 c, v dd =5v 5%, v ee =-5v 5%, v ref =2.5v 0.5%, gnda=gndd=0v, clock frequency = 2.048mhz, filter gain setting = 0db. outputs unloaded unless otherwise specified. characteristics sym. min. typ. * max. units test conditions 1 a n a l o g analog output at v r equivalent to the overload decision level at codec v out 4.829 5.000 v pp v pp level at codec: - law: 3.17 dbm0 a-law: 3.14 dbm0 r l =10 k ? see note 7 2 absolute gain (0db setting) g ar -0.25 +0.25 db 0 dbm0 @ 1004hz 3 absolute attenuation (-1db to -7db settings) -0.35 +0.35 db from nominal, @ 1004hz 4 gain variation with temp. g art 0.01 db t a =0 c to 70 c with supplies g ars 0.04 db/v 5 gain tracking ccitt g712 (see figure 12) (method 1) gt r1 -0.25 -0.25 -0.50 +0.25 +0.25 +0.50 db db db sinusoidal level: +3 to -10 dbm0 noise signal level: -10 to -55 dbm0 -55 to -60 dbm0 ccitt g712 (method 2) at & t gt r2 -0.25 -0.50 -1.50 +0.25 +0.50 +1.50 db db db sinusoidal level: +3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 6 quantization ccitt g712 distortion (method 1) (see fig. 13) d qr1 28.00 35.60 33.90 29.30 14.30 db db db db db noise signal level: -3 dbm0 -6 to -27 dbm0 -34 dbm0 -40 dbm0 -55 dbm0 ccitt g712 (method 2) at & t d qr2 36.40 30.40 25.40 db db db sinusoidal input level: 0 to -30 dbm0 -40 dbm0 -45 dbm0 7 idle channel c-message n cr 12 dbrnc0 - law only noise psophometric n pr -75 dbm0p ccitt g712 8 single frequency noise n sfr -56 dbm0 ccitt g712 9 harmonic distortion (2nd or 3rd harmonic) -46 db input signal 0 dbm0 at 1.02 khz 10 intermodulation ccitt g712 distortion 2 tone imd r2 -41 db at & t imd r3 -47 db 2nd order products 4 tone imd r4 -49 db 3rd order products
mt8960/61/62/63/64/65/66/67 data sheet 20 zarlink semiconductor inc. * typical figures are at 25 c with nominal 5v supplies. for design aid only: not guaranteed and not subject to production testing. note 7: 0dbm0=1.185 v rms for - law codec and 0dbm0=1.231 v rms for a-law codec. 11 a n a l o g envelope delay d ar 210 s @ 1004 hz 12 envelope delay 1000-2600 hz variation with 600-3000 hz frequency 400-3200 hz d dr 90 170 265 s s s input signal: 400 - 3200 hz digital sinewave at 0 dbm0 13 gain relative to < 200 hz gain @ 1004 hz 200 hz (see figure 11) 300-3000 hz 3300 hz 3400 hz 4000 hz 4600 hz g rr -0.5 -0.125 -0.350 -0.80 0.125 0.125 0.125 0.030 -0.100 -14.0 -28.0 db db db db db db db 0 dbm0 input signal receive filter response 14 crosstalk a/d to d/a ct tr -70 db 0 dbm0 @ 1.02 khz in a/d 15 power supply v dd rejection v ee psrr 3 psrr 4 33 35 db db input 50 mv rms at 1.02 khz 16 overload distortion (see fig. 15) input frequency=1.02 khz ac electrical characteristics - receive (d/a) path - voltages are with respect to gndd unless otherwise stated. t a =0 to 70 c, v dd =5v 5%, v ee =-5v 5%, v ref =2.5v 0.5%, gnda=gndd=0v, clock frequency = 2.048mhz, filter gain setting = 0db. outputs unloaded unless otherwise specified.
mt8960/61/62/63/64/65/66/67 data sheet 21 zarlink semiconductor inc. figure 9a - timing diagram - 125 s frame period c2i input f1i internal enable dsto output dsti input ca csti input load a-register load b-register 125 s 76543210 76543210 76543210 high impedance 7 7 76 6 76543210 5 v 0 v (mode 3)
mt8960/61/62/63/64/65/66/67 data sheet 22 zarlink semiconductor inc. figure 9b - timing diagram - output enable note: in typical applications, f1i will remain low for 8 cycles of c2i. however, the device will fu nction normally as long as t es and t eh are met at each positive edge of c2i. figure 9c - timing diagram - input/output c2i input f1i input dsto output high impedance 8 clock cycles (see note) 90% 50% 10% 90% 10% t ef t es t eh t pzl t pzh t cr t cf t er t es t eh t pzl t pzh t es t eh high-z 90% 50% 10% 90% 50% 10% 90% 50% 10% c2i input dsto output dsti, csti input t cr t cf t or t of t plh t if t ir t ih t ish t isl t plh
mt8960/61/62/63/64/65/66/67 data sheet 23 zarlink semiconductor inc. figure 10 - attenuation vs frequency for transmit (a/d) filter attenuation relative to attenuation at 1 khz (db) scale b scale a passband attenuation scale b scale a 0 10 20 25 30 40 -0.125 0.35 1 2 3 4 0 5060 100 200 300 3000 3200 3300 3400 4000 4600 5000 10000 0.125 0.35 1 2 3 4 10 14 20 30 32 40 stopband attenuation -0.125 -14 -18 sin sin (4000-f) 1200 (4000-f) 1200 - 1 -7/9 note: above function crossover occurs at 4000hz. frequency (hz)
mt8960/61/62/63/64/65/66/67 data sheet 24 zarlink semiconductor inc. figure 11 - attenuation vs frequency for receive (d/a) filter attenuation relative to attenuation at 1 khz (db) 0 1 2 3 4 scale a passband attenuation scale b scale a 0.125 0.35 1 2 3 4 -0.125 0 100 200 300 3000 3200 3300 3400 4000 4600 5000 10000 -14 sin (4000-f) 1200 - 1 stopband attenuation frequency (hz) 10 14 20 28 30 40
mt8960/61/62/63/64/65/66/67 data sheet 25 zarlink semiconductor inc. figure 12 - variation of gain with input level +1.0 +0.5 +0.25 0 -0.25 -0.5 -1.0 -60 -55 -50 -40 -30 -20 -10 5a. ccitt method 1 ccitt end-to-end spec bandlimited white noise test signal +1.0 +0.5 +0.25 0 -0.25 -0.5 -1.0 -10 0 -3 sinusiodal test signal 1 2 channel spec input level (dbm0) +1.5 +1.0 +0.5 0 -0.25 -0.5 -1.0 -1.5 +0.25 -60 -50 -40 -30 -20 -10 0 +3 ccitt end-to-end spec 1 2 channel spec input level (dbm0) sinusoidal test signal 5b. ccitt method 2 gain variation (db) gain variation (db)
mt8960/61/62/63/64/65/66/67 data sheet 26 zarlink semiconductor inc. figure 13 - signal to total distortion ratio vs input level 40 30 20 10 0 -60 -55 -50 -34 -30 -27 -20 -10 -6 -3 0 +3 -40 14.3 12.6 29.3 27.6 33.9 32.2 35.6 33.9 26.3 28.0 input level (dbm0) 1 2 channel spec ccitt end-to-end spec 6a. ccitt method 1 40 30 20 10 0 -60 -50 -40 -30 -20 -10 0 24.3 25.4 30.4 36.4 36.4 29.3 35.3 35.3 22.0 27.0 33.0 33.0 1 2 channel spec d/a 1 2 channel spec a/d ccitt end-to-end spec input level (dbm0) 6b. ccitt method 2 signal to total distortion ratio (db) signal to total distortion ratio (db)
mt8960/61/62/63/64/65/66/67 data sheet 27 zarlink semiconductor inc. figure 14 - envelope delay variation frequency 1000 750 500 370 250 125 0 500 1000 1500 2000 2500 3000 (600hz) (2800hz) (2600hz) ccitt ? channel spec envelope delay ( s)
mt8960/61/62/63/64/65/66/67 data sheet 28 zarlink semiconductor inc. figure 15 - overload distortion (end-to-end) 5 4.5 4 3 3456789 input level (dbm0) *relative to fundamental output power level with +3 db m0 input signal level at a frequency of 1.02 khz. fundamental output power (dbm0)*

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